1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device having a function of inhibiting erroneous erasing of electrically and collectively erasable flash EEPROM (Electrically Erasable and Programmable Read Only Memory).
2. Description of the Background Art
FIG. 10 is a schematic block diagram of a conventional flash EEPROM. The flash EEPROM shown in FIG. 10 is disclosed in "IEEE Journal of Solid-State Circuits" Vol. 23, No. 5, pp. 1157-1163, October 1988. Referring to FIG. 10, provided on the periphery of a memory cell array 1 are a Y gate 2, a source line switch 3, an X decoder 4 and a Y decoder 5. The X decoder 4 and the Y decoder 5 are connected to an address register 6 to which address signals are externally inputted. A writing circuit 7 and a sense amplifier 8 are connected to the memory cell array 1 through the Y gate 2. The writing circuit 7 and the sense amplifier 8 are connected to an input/output buffer 9.
A program voltage generating circuit 10 and a verify voltage generating circuit 11 are provided for generating voltages different from externally applied power supplies Vcc and Vpp and applying the same to the Y gate 2 and the X decoder 4. A command register 12 and a command decoder 13 are provided which set an operation mode in response to the externally inputted data and a control circuit 14 receives externally applied control signals WE, CE and OE.
FIG. 11 is a sectional view of the memory cell shown in FIG. 10. Referring to FIG. 11, the memory cell comprises a floating gate 16 formed on a semiconductor substrate 15, a control gate 17, a source diffusion region 18 and a drain diffusion region 19. An oxide film between the floating gate 16 and the substrate 15 is as thin as about 100 .ANG., enabling tunneling of the electrons in the floating gate 16 by Fowler-Nordheim tunneling mechanism. The memory cell 1 operates as follows. Namely, during the programming, a program voltage of about 6.5 V is applied to the drain 19 and Vpp (12 V) is applied to the control gate 17, and the source 18 is grounded. Hot electrons are injected into the floating gate in the same manner as in EPROM's. The threshold voltage of the memory cell 1 is increased in this way. This is defined as the storage of the information "0".
Conversely, erasing is carried out by disconnecting the drain 19 and grounding the control gate 17 to apply the Vpp to the source 18. The Fowler-Nordheim tunneling occurs due to a potential difference between the source 18 and the floating gate 16, whereby the electrons in the floating gate 16 are emitted. The threshold voltage of the memory cell 1 is lowered in this way, which is defined as the storage of the information "1".
FIG. 12 is a diagram showing the structure of the memory cell array shown in FIG. 10, assuming that the memory cell array includes 9 memory cells. Referring to FIG. 12, drains of three memory cells are connected to a bit line and control gates of the three memory cells are connected to a word line. The word line 25 is connected to the X decoder 4 and the bit line 24 is connected to an I/O line 27 through an Y gate transistor 26 having a gate receiving the output of the Y decoder 5. The I/O line 27 is connected to the sense amplifier 8 and the writing circuit 7 and a source line 28 is connected to the source line switch 3.
Description will be made of an operation of a conventional flash EEPROM with reference to FIGS. 10 through 12. First, an operation will be described in a case where data is written in the memory cell 1 encircled by a dotted line shown in FIG. 12. The writing circuit 7 is activated in response to externally inputted data, so that the program voltage is supplied to the I/O line 27. At the same time, the Y gate 26 and the word line 25 are selected by the Y decoder 5 and the X decoder 4, respectively, by using the address signals, so that the Vpp is applied to the memory cell 1. The source line 28 is grounded by the source line switch 3 during the programming. In this way, current flows to only a single cell in FIG. 12, whereby hot electrons are generated and the threshold voltage thereof is increased.
Conversely, erase is carried out as follows. First, the X decoder 4 and the Y decoder 5 are inactivated, thereby causing all the memory cells 1 to enter a non-selected state. Namely, all the word lines of each memory cell are grounded and the drains are disconnected. Meanwhile, a high voltage is applied to the source line 28 by the source line switch 3. The threshold voltages of the memory cells shift to a lower level due to the tunneling phenomenon. Since the source line 28 is shared, erase is made for all the memory cells.
A read operation will be described. Similarly to the writing operation, reading the memory cell encircled by the dotted line of FIG. 12 will be described. First, the address signals are decoded by the Y decoder 5 and the X decoder 4, so that the output of selected Y gate 26 and the word line 25 attain the "H" (logical high) level. At this time, the source line 28 is grounded by the source line switch 3. In the case where the memory cell is programmed, even if the "H" level signal is applied to the control gate of the memory cell from the word line 25, the memory cell is not turned on, whereby no current flows from the bit line 24 to the source line 28.
Conversely, when a memory cell is erased, the memory cell is turned on, whereby current flows from the bit line 24 to the source line 28. The sense amplifier 8 detects whether or not the current flows through the memory cell to obtain the read data "1" or "0". Data writing and reading of the flash EEPROM are performed in this way.
Meanwhile, another example of an ROM is an EPROM allowing data to be erased by irradiating ultra-violet rays. In such an EPROM, when a floating gate becomes electrically neutral, no more electron is emitted from the floating gate, so that a threshold voltage of a memory transistor never becomes less than about 1 V. In the tunneling phenomenon, the electrons are excessively emitted from the floating gate, so that the floating gate might be charged to be positive. This phenomenon is referred to as over-erase or over-erasure.
If the threshold voltage of the memory transistor becomes negative, the following reading and writing will be adversely affected. Namely, in the reading, even if a word line level is unselected, current flows from the bit line 24 through the over-erased memory transistor. In this case, when the memory cell, which is programmed successfully, is selected, ".phi." can not be read out because of the current flow of an over-erased cell. In addition, since leakage current flows through a over-erased memory cell during the writing, the writing characteristics are deteriorated, disturbing the writing.
Therefore, there is a method of preventing memory cells from excessive-erasing by reading after the erase to verify whether the erase is properly done or not (referred to as erase verify, hereinafter) and erase again when there is a bit which is not erased.
FIG. 13 shows flow charts of erase and program including the above-described verifying operation and FIGS. 14A and 14B are timing charts showing both operations.
Referring to FIGS. 10, 13, 14A and 14B, programming and erasing operations will be described. In the conventional flash EEPROM, program and erase modes are set by a combination of input data. Namely, mode setting is carried out by the data at the rise of the write enable signal WE. First program will be described with reference to FIG. 14A. First, Vcc and Vpp are caused to rise in step (abbreviated to S in the drawings) S1 and then, the write enable signal WE is caused to fall in step S2. Thereafter, input data 40.sub.H is latched in the command register 12 at the rise of the write enable signal WE. Then, the input data is decoded by the command decoder 13, changing the operation mode to the program mode.
Then, in step S3, the write enable signal WE is again caused to fall and the external address signals are latched in the address register 6, then the data is latched in the writing circuit 7 at the rise of the write enable signal WE. Then, the program pulse is generated from the program voltage generating circuit 10 and applied to the X decoder 4 and the Y decoder 5. The programming is carried out in this way.
Then, the write enable signal WE is caused to fall and the input data (CO.sub.H) is inputted and latched in the command register 12. Subsequently, at the same time as the rise of the write enable signal WE, the operation mode changes to the program verification mode (S6). At this time, the program verify voltage (.about.6.5 V) is generated in the chip by the verify voltage generating circuit 11 and applied to the X decoder 4 and the Y decoder 5. As a result, the voltage applied to the control gate of the memory cells becomes higher than that in the ordinary reading (.about.5 V), so that the memory transistors having insufficient threshold voltage shift turn on (data "1"), allowing detection of defective programming.
Then, reading is carried out to check the programmed data in step S7. If the determination is made in step S8 that the programming is false, processings are further carried out in steps S2-S7 to complete programming. If the program is done, the reading mode is set in step S9 to complete the programming.
Referring to FIG. 14B, an erase operation will be described. First in step S10, Vcc and Vpp are caused to rise and subsequently, "0" is programmed in all the bits in accordance with the above-described program flow processing in step S11. This is because, if the erased memory cells are further erased, one of memory cells in the memory cell array 1 might be over-erased. Then, the write enable signal WE is caused to fall to input the erase command. Namely, (20.sub.H) is inputted in step S12. Subsequently in step S13, command inputting is carried out to start the erase and the erase pulse is internally generated at the same time as the rise of the write enable signal WE. Namely, Vpp is applied to the sources of the memory cells through the source line switch 3. Thereafter, Vpp is applied to the source line 28 until the next falling of the write enable signal WE. At the same time, the addresses are also latched in the address register 6 at the falling edge. In step S15, the erase verify command (AO.sub.H) is inputted at the rise of the write enable signal WE to set the erasing verification mode.
In the erasing verification mode, the erase verify voltage (.about.3.2 V) is applied to the X decoder 4 and the Y gate 2 by the verify voltage generating circuit 11. As a result, the voltage applied to the control gates of the memory cells becomes lower than that (5 V) in the ordinary reading, so that insufficiently erased memory cells do not readily turn on (data "0").
Then, in step S16, reading is carried out to actually verify the erase. In step S17, if it is determined that the erase is insufficiently done, the erase is further repeated and if the erase is sufficiently done, the address is incremented to verify the erasing data of the next address in the step S18. If it is determined in step S19 that the verified address is the last, the operation mode is changed to the reading mode in step S20 to complete a series of operations.
Prior to shipment of the conventional flash EEPROM structured as described above, "0" should be surely written in all the bits or reading should be carried out to verify that all the bits are "0" before erase.
A user of the flash EEPROM might erroneously perform an erasing operation on the device which requires no further erase. This results in over-erase of the device.